1. Field of the Invention
The present invention relates to a graphics drawing image processing apparatus and, more particularly, relates to a refresh technique of a built-in memory when accommodating a dynamic random access memory (DRAM) or other memory requiring refreshing and a logic circuit.
2. Description of the Related Art
Computer graphics are often used in a variety of computer aided design (CAD) systems and amusement machines. Especially, along with the recent advances in image processing techniques, systems using three-dimensional computer graphics are becoming rapidly widespread.
In three-dimensional computer graphics, the color value of each pixel is calculated at the time of deciding the color of each corresponding pixel. Then, rendering is performed for writing the calculated value of the pixel to an address of a display buffer (frame buffer) corresponding to the pixel.
One of the rendering methods is polygon rendering. In this method, a three-dimensional model is expressed as a composite of triangular unit graphics (polygons). By drawing the polygons as units, the colors of the display screen are decided.
In polygon rendering, coordinates (x, y, z), color data (R, G, B), homogeneous coordinates (s, t) of texture data indicating a composite image pattern and a value of the homogeneous term q for each vertex of the triangle in a physical coordinate system are input, and processing is performed for interpolation of these values inside the triangle.
Here, looking at the homogeneous term q, the coordinates in a UV coordinate system of an actual texture buffer, namely, texture coordinate data (u, v), are comprised of the homogeneous coordinates (s, t) divided by the homogeneous term q to give “s/q” and “t/q”, which in turn are multiplied by texture sizes USIZE and VSIZE, respectively.
FIG. 21 is a view of the system configuration showing the basic concept of a three-dimensional computer graphics system.
In this three-dimensional computer graphics system, data for drawing graphics is supplied from a main memory 2 in a main processor 1 or from an input/output (I/O) interface circuit 3 for receiving graphic data from the outside via a main bus 4 to a rendering circuit 5 having a rendering processor 5a and a frame buffer memory 5b. 
In the rendering processor 5a, a frame buffer memory 5b for holding data for display and a texture memory 6 for holding texture data to be applied on the surface of a graphic element (for example, a triangle) to be drawn are connected.
Then, the rendering processor 5a performs processing for drawing the graphic element applied with the texture on its surface for every graphic element in the frame buffer memory 5b. 
The frame buffer memory 5b and the texture memory 6 are generally configured by a DRAM.
In the system of FIG. 21, the frame buffer memory 5b and the texture memory 6 are configured as physically separated memory systems.
In a graphics drawing image processing apparatus, however, the memory is frequently accessed, such as for writing and reading image data to and from the memory and for reading for display of the image. Further, it is necessary that a wide bus width of the memory be secured to obtain the full graphic drawing performance.
As a result, it has become physically impossible to separately arrange the graphics drawing image processing apparatus and memory due to the increase of the number of interconnections, so the DRAM and the logic circuit began to be accommodated on one chip.
Since a DRAM built-in on the same chip with the logic circuit uses capacitors for memory elements of memory cells, when a certain time passes, data stored in the capacitors of the memory cells as charges are lost due to leakage current or other disturbances.
Thus, as is well known, a refresh operation is performed based on a predetermined system on the DRAM to rewrite and maintain the data held by the memory cells.
Taking a 1 Megabit DRAM as an example, when one line address (page address) is selected, at the time of a refresh operation, the 2048 cells connected to the selected word line are refreshed simultaneously.
The standard of a refresh operation is, for example, calls for performing a refresh operation 512 cycles in 8 ms. All of the 512×2048=1M bits worth of cells are refreshed by this number of cycles.
As the systems for refreshing a DRAM, there are mainly the line refresh method shown in FIG. 22A and the burst refresh method shown in FIG. 22B.
Further, as a system for refreshing a memory for graphics, for example, as shown in FIG. 22C, the system is adopted of performing a number of refresh operations satisfying the standard for refresh operations in units of the horizontal synchronization signal HSYNC.
As explained above, in the graphics drawing image processing apparatus, it became easy to secure the bus width by arranging the memory inside the LSI.
However, the refresh operation causes the following disadvantages when making the built-in DRAM larger in capacity to improve the performance.
First, a refresh operation of a DRAM consumes a large amount of power, so the circuit is liable to stop operating normally if the operation is performed all at once due to the fluctuation in a power due to a voltage drop or noise.
Second, performing the refresh operation of a large scale DRAM all at once causes a large current to flow and may damage the device.
Third, it is difficult to judge whether a malfunction in a large-scale circuit is caused by a refresh operation or another reason.
Fourth, when a malfunction can be judged to be caused by a refresh operation, it may be difficult to check and measure the operation of the chip without a refresh operation and may become necessary to remake the chip with countermeasures.
Finally, fifth, even when the circuit does not malfunction, it becomes necessary to use a heat resistant ceramic or other package able to withstand the instantaneous power consumption at the time of a refresh operation, so the cost becomes higher compared with the case of using a plastic package.